Advances in technology have provided electronic devices such as battery-powered and/or mobile electronic devices, personal digital assistants (PDA) and laptop or notebook computers with an increased integration level and computing power. As portable devices generally draw power from one or more batteries, various power management or power conservation techniques have been implemented in order to increase or maximize work time of the portable devices. Particularly, reducing power consumption of a central processing unit (CPU) that generally has the highest integration level may be desirable in decreasing system power consumption. In addition, it may be desirable to modify the power consumption of the CPU according to an operational mode of the CPU, which determines an operation mode of the electronic device.
The operational mode of the CPU has an active mode (or a normal mode) and an idle mode (or a standby mode). In a general portable device, the work time in the idle mode may be above 90% of total work time, on average. Therefore, to reduce power consumption, the current consumption in the idle mode may be reduced. A method of reducing the power consumption in the idle mode may be desirable because the overall system operation may not be affected when operated with a reduced performance level in the idle mode, whereas the system performance may be a major concern in the active mode.
FIG. 1 is a schematic view illustrating an exemplary configuration of an electronic device, such as a portable device.
Referring to FIG. 1, the device 100 generally includes a central processing unit (CPU) 100, a main system bus 120 coupled to the CPU 100 and a secondary bus (or a peripheral bus) 140 to which a low-speed peripheral device 170 is coupled. The main system bus 120 is coupled to the secondary bus 140 through a bus bridge 130 and slave devices 160 and 170 are coupled to the main system bus 120 and the secondary bus 140, respectively. When the mobile device is to be equipped with a display to represent images, a display device 150 may be connected to the system bus 120 or the secondary bus 140 as the slave device. In FIG. 1, the display device 150 is shown connected to the main system bus 120.
Based on a given clock division ratio of each component device, a predetermined reference clock frequency may be divided and provided to the respective devices of the mobile device 100 as an operation clock frequency. The component elements shown in FIG. 1 may be all integrated into a single chip to reduce or minimize the entire system size and power consumption. Alternatively, one or more of the component elements may be implemented on a separate chip. For example, in an S3c2440 CPU having an ARM920T core of Advanced RISC Machines (ARM) Co., most of the components are implemented on a single chip.
One method of decreasing the current consumption in the idle mode of the CPU is to power off a clock frequency of the CPU. Namely, in the idle mode, the clock frequency applied to the CPU may be set to be ‘0’. However, this method may be problematic since the clock frequencies of the main system bus and the secondary bus remain the same so that the amount of reduced current of the entire system may be minor. Moreover, if the clocks of the main system bus and the secondary bus are also powered off in the idle mode, the slave devices connected to the bus may not operate properly. Particularly, in the display devices, which periodically refresh the screen in each refresh cycle, clock management may need to be cautiously performed so as not to affect a normal display of the display devices.